Increased circuit density is an ongoing goal of manufacturers of semiconductor devices. One favored configuration to increase circuit density is an assembly of vertically stacked semiconductor dice, at least some of which are interconnected electrically, the stacked die assembly being mechanically and electrically connected to higher level packaging, such as an interposer or other substrate bearing conductive traces.
One such configuration employing a plurality of stacked semiconductor dice is a Micropillar Grid Array (“MPGA”) package. Such a package comprises a stack of a plurality (for example, four (4), eight (8), sixteen (16), etc.) of dynamic random access memory (DRAM) dice vertically interconnected from an uppermost die to a lowermost die, and a plurality of electrically conductive pillars extending from the underside of the lowermost memory die for connection to a logic die, such as, by way of non-limiting example, a System on a Chip (SoC) die.
A challenge associated with stacked die packages is that the heat generated by the individual dies and associated circuitry combines and increases the operating temperatures of the individual dies, the junctions therebetween, and the package as a whole. This can cause the stacked dies to reach temperatures above their maximum operating temperatures (Tmax), especially as the density of the dies in the package increases.
Another challenge associated with stacked die packages is the formation of oxide-induced stresses on a back side of semiconductor dice that make up the stacked die package. Dielectric materials on the back side of the semiconductor dice that isolate conductive portions of the dice from the substrate thereof often induce stresses in the substrate.
Accordingly, one significant focus with regard to formation of such stacked die packages is effective thermal management of heat generated during operation by stacked memory dice of the die assembly, in combination with heat generated by a logic or SoC die at the base of the die assembly so that the maximum operational temperature of each die within the package does not exceed acceptable limits. Another focus is the effective management and reduction of induced stresses that cause wafer warpage (e.g., bowing) of the semiconductor structures, which inhibits the ability of transfer and process equipment to handle wafers effectively and without damage, as well as impairing yield of wafer-level processing techniques used to form stacked die assemblies.